1. Technical Field
Various embodiments of the present invention relate to clock signal generation circuits. In particular, certain embodiments relate to a clock signal generation circuit for generating a clock signal with a desired period from an input clock signal.
2. Related Art
A semiconductor integrated circuit typically operates in synchronization with a clock signal. The clock signal may be input from outside of the semiconductor integrated circuit, or may be generated through a clock generator in the semiconductor integrated circuit. Since the semiconductor integrated circuit performs various operations, it is not possible to perform all operations using only one clock signal with a constant period. Therefore, a circuit for generating a clock signal with a desired period from a clock signal with a reference period is required.
FIG. 1 is a diagram schematically illustrating a configuration of a clock multiplier generally used. In FIG. 1, the clock multiplier includes a delay Delay and an exclusive OR gate XOR. The delay Delay delays an input clock signal CLK_IN and the exclusive OR gate XOR performs an XOR operation on the input clock signal CLK_IN and the output A of the delay Delay to generate an output clock signal CLK_OUT. When the delay amount of the delay Delay is set to one-quarter (¼) of one period of the input clock signal CLK_IN, a phase difference of ninety degrees (90°) occurs between the input clock signal CLK_IN and the output A of the delay Delay. Consequently, it is possible to generate the output clock signal CLK_OUT with a frequency (a period of ½) that is twice as high as the frequency of the input clock signal CLK_IN through the operation of the exclusive OR gate XOR.
FIG. 2 is a diagram schematically illustrating the configuration of another clock multiplier in the conventional art. In FIG. 2, the clock multiplier includes an oscillator 10, a counter 20, and a logic circuit 30. The oscillator 10 continuously generates a periodic signal OSC with a frequency higher than a frequency of an input clock signal CLK_IN. The counter 20 receives the input clock signal CLK_IN and counts the number of toggles of the periodic signal OSC for one period of the input clock signal CLK_IN. The logic circuit 30 receives the output of the counter 20 and the periodic signal OSC. The logic circuit 30 continuously generates a clock signal with a pulse width corresponding to ½ of the counted value of the counter 20 from the periodic signal OSC, thereby generating an output clock signal CLK_OUT with a frequency that is twice as high as the frequency of the input clock signal CLK_IN.
However, the clock multipliers in the conventional art have the following problems. The clock multiplier illustrated in FIG. 1 has the simplest configuration. However, the duty ratio of the output clock signal may change significantly according to the amount and degree of delay. Furthermore, when the duty ratio of the input clock signal is not constant, jitter of the output clock signal may increase.
The clock multiplier illustrated in FIG. 2 has an advantage of being capable of reducing a change in the phase and the duty ratio. However, current consumption may increase according to the continuous use of the oscillator and an increase in the frequency of the periodic signal, and the areas of the counter and the logic circuit may significantly increase according to the bits of the counter.